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RISC Processor, Custom ISA, and compiler2026-4-4Over spring break, I put together a simple 32 bit RISC (reduced instruction set computer) processor using Logisim in order to follow along with the architecture described in the book Computer Architecture: A Quantitative Approach. Since the goal was primarily to study higher level computer architecture, not every component was built from logic gates and I made heavy use of the built in multiplexers. To have something to run on the processor, I also wrote a compiler for a custom object oriented programming language which compiles down to an intermediate language based on the stack based VM from the Nand2Tetris series. I implemented a second compiler which will go from this intermediate language down to my own assembly language.
This project is most certainly not finished and I would like to continue to add onto it as I continue to go through the book. The compiler also has basically no optimization as of now and I look forward to making it more efficient. Most of the project is documented on its GitHub page (https://github.com/sustachio/reduced-reduced-instruction-set-computer-and-compiler), so not everything will be discussed here. Nonetheless, the basic features include:
No speculative branch prediction has been implemented yet so the compiler must insert 3 nops after each jump or conditional branch to prevent instructions following a successful jump in memory from being executed. Rubellite programming languageI've always wanted to write a compiler from scratch and this project seemed like the perfect excuse to do so. The language (which I've dubbed
In this example, Although not demonstrated here, you can have The language itself is tokenized and then parsed into an abstract syntax tree. This then compiles down to a slightly modified version of the intermediate language from the Nand2Tetris series which is just a stack based VM. Since I wrote all of the code to manage function calls and returns on the stack when implementing the intermediate language, it made the full language much easier to write. I will likely move away from this intermediate language and go straight to assembly as it is proving to make it more difficult to optimize the compiler. Final remarksI'm looking forwards to expanding this processor and potentially reworking it to allow for some sort of instruction scheduling. There is a full devlog on the GitHub readme, but I will include a small log for changes made to this article here.
If you are looking to learn about some computer architecture, I'd strongly recommend you also read Computer Architecture: A Quantitative Approach, as it has proven to be a very in-depth and informative text. The processor in the initial version of this post is just based on the content in Appendix C which was just a review of pipelined processors. Thank you for reading and have a wonderful day! ^_^ CommentsPost a comment:Please don't spam the comments, I get a notification every time. Also please be mature (Nolan) Message limit: 1500 characters, name limit: 100 characters |
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